In an NRZ data stream, a data pulse stays at one level or another for the entire duration of a bit interval, i.e., for one full clock cycle. For example, a sequence of three consecutive 1's is presented by a constant level signal lasting three bit intervals, or three clock cycles. This is in contrast to an RZ (return-to-zero) data stream wherein a digital 1 is represented by a pulse which does not last the entire bit interval but rather returns to zero. For example, a sequence of three consecutive 1's in an RZ data stream is presented by three consecutive distinct pulses, each lasting one-half bit interval or clock cycle and returning to zero for the remainder of its clock cycle.
In both NRZ and RZ data streams, it is necessary to have a train of clock pulses providing timing information for demarcation of bit intervals in the identification of 1's and 0's in the data stream. In a communication system, it may be necessary to derive or "recover" clock pulses from the occurrence of the received data pulses.
One kind of circuit used to recover clock pulses from a data stream is a phase locked loop. In this type of circuit, a voltage controlled oscillator (VCO) generates clock pulses which are fed together with received data pulses to a phase detector. The phase detector generates a voltage which is some function of the difference in phase between the data and the clock. The voltage from the phase detector drives the voltage controlled oscillator to produce clock pulses which stay in phase with the data pulses.
There are various types of apparatus for deriving clock pulses from RZ data, and include a variety of phase detectors. In one type of phase detector for RZ data, a measuring interval is initiated by a data transition and is terminated by the opposite data transition one-half clock cycle later. The relative time of occurrence of a clock transition within this measuring interval gives an indication of the phase difference between the data and the clock. The duration from a rising data edge to a clock transition is compared against the duration from that clock transition to the falling data edge, and the duration difference corresponds to phase differential. Since each data pulse returns to zero during its bit interval, the falling data edge transition may be used to terminate the measuring interval.
In an NRZ data stream, the falling data edge transition may not be used to terminate the measuring interval because it is not known when such transition will occur. For example, if the next bit is a zero, then the data will transit low at the end of the current bit interval; but if the next data bit is a 1, then the data will stay high and no data edge transition will occur at the end of the current bit interval. In an RZ data stream, a data 1 transits high and then low all within one bit interval (the data pulse has a duration of one-half clock cycle). If the next data bit is also a 1 then the data will again transit high and then low. The falling data edge in an RZ data stream may thus be used to terminate the measuring interval because it is known that such edge transition will occur within the bit interval and one-half clock cycle after the rising data edge. In an NRZ data stream, the time of occurrence of the falling data edge is indeterminate and hence not suitable for providing a known relative timing reference.
Various phase detection schemes have been attempted for NRZ data. An analog approach to NRZ data phase detection involves the use of a differentiator receiving NRZ data and generating positive and negative analog pulses in response to data edges. These analog pulses are typically half or full wave rectified and then fed together with recovered clock pulses to a multiplier mixer whose output is the phase error control to the VCO. This multiplier mixer is typically complex and expensive, particularly at high frequency data rates where transformers may become necessary.
A digital approach to NRZ data phase detection involves the use of a monostable one-shot multivibrator for receiving NRZ data and converting data edges to unidirectional digital pulses. These digital pulses are fed together with recovered clock pulses to a multiplier such as an exclusive OR gate, whose output is the phase error control to the VCO. This multiplier is simpler and less expensive than the above noted analog multiplier. However, a number of problems are presented with the use of the one-shot multivibrator. One-shot multivibrators are prone to variation in output pulse width due to temperature and aging. This affects the clock and data phase relationship and may cause errors in retiming the data with the recovered clock. The pulse width generally becomes a greater problem as the data rate increases, since factors affecting timing become more critical. The phase of the recovered clock in many applications requires correction in order to retime the data correctly. Furthermore, since the one-shot multivibrator produces a pulse of fixed width, the pulse width must be adjusted to the data rate at which the phase detector is to be used.
A digital NRZ data phase detector which solves the above problems has been provided by phase error circuitry which generates a measuring interval initiated by a data transition and terminated not by the opposite data transition, but rather by a clock transition. Termination of the measuring interval is not dependent upon the indeterminate time of occurrence of a falling data edge in an NRZ data stream. The measuring interval is composed of a variable duration subinterval and a fixed duration subinterval. The variable duration subinterval is provided by a variable duration pulse which is generated with a length equal to the time between a data transition and a given clock transition. The fixed duration subinterval is provided by a fixed duration pulse which is generated with a length equal to the duration between the given clock transition and the immediately succeeding clock transition of opposite polarity. The fixed duration pulse has a length equal to the duration of one clock pulse, i.e., one-half clock cycle.
The latter mentioned NRZ digital data phase detector has a first gate responsive to incoming NRZ data, and a second gate responsive to the output of the first gate and to the clock. Output logic gating circuitry responds to the outputs of the first and second gates and generates the variable duration pulse and then the fixed duration pulse. This output gating circuitry initiates the variable duration pulse and the measuring interval concurrently in response to the data transition. In response to the next clock transition of one polarity, the output gating circuitry terminates the variable duration pulse and simultaneously initiates the fixed duration pulse. In response to the immediately succeeding clock transition of opposite polarity, the output gating circuitry terminates the fixed duration pulse and the measuring interval.
The present invention relates to improvements over the latter mentioned NRZ digital data phase detector. One improvement involves circuit simplification and elimination of the output gating circuitry. Another improvement involves expansion of the measuring interval, enabling slower speed components to be used.